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WARP FPGA Board v2.1 to v2.2 Pin Definitions


The supply of WARP boards is limited, however there is a small number of version 2.1 FPGA boards that I’ve stumbled across. The only problem is that the basic OFDM reference model will not work with these boards since there was an error in their design, causing some of the pins to be routed differently. I believe there is a problem with one of the clock pins (it’s not buffered correctly on the FPGA) that prevents one of the components from working.


The OFDM reference model IS compatible with the v2.1 FPGA WARP board, however some pin changes need to be made in the user constraint file. This can be edited from the Xilinx Project EDK in the left-hand side window. It’s the file listed there that ends in .ucf. The following pin changes need to be made:

Pin Name v2.1 v2.2
GMII_CRS_0 J22 H24
clk_board_logic_D0 AM22 AR21
radio3_ADC_I3_pin AR21 AM22
radio4_ADC_I3_pin AE22 AF23
analog4_LED2_pin AE22 AF23


This effects the following blocks: Hard TEMAC Ports, Clock Board, Radio Bridge, Analog Bridge.

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